1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device such as a flash memory of channel hot electron write type.
2. Description of the Related Art
Up to the present, in a flash memory of channel hot electron type write system, the end point of write is determined by verifying through monitoring, at the time of write, the threshold voltage of the memory cell write current flowing between the drain and the source (drain current), as disclosed, for example, in U.S. Pat. No. 5,422,842.
Referring to FIG. 1 showing a conventional circuit, the situation mentioned above will be described in more detail. At the time of write, a voltage of, for example, 12V is supplied to the control gate of a cell transistor of a memory cell array 3 from a word signal line D. A write current detection type write circuit 2 supplies a drain voltage necessary for write, a voltage of 6V, for example, to the drain of a transistor 21. A comparator circuit 23 compares a current Icell (drain current) flowing between the drain and the source of a cell transistor of the memory cell array 3 due to the drain voltage against a reference current Iref for detecting the end of write. As the threshold voltage of the cell transistor falls with the progress in writing, the current Icell also falls until the current Icell becomes equal to the reference current Iref for detecting the end of write. The comparator circuit 23 detects this point as the end of write, and outputs a matching detection signal E. The signal E is input to a control circuit 4 to inactivate a write control signal A supplied to the gates of the transistors 21 and 22, and turns off the transistor 21 and 22 and turns on the transistor 24 to stop the writing.
The arrangement described above is referred to as the write current detection type write system. In this system, it is possible to perform writing at high speed since the need for providing a time for verifying the threshold voltage of the memory cell transistor, separately from the write time, can be eliminated as the drain current is monitored in parallel while writing is in progress.
However, in the conventional write current detection type write system, it is difficult to precisely match the detection time of an end of write with the actual time of a stop of write. Moreover, because of the high rate of write, overshoot in writing takes place corresponding to the mismatch between the detection time of the end of write and the actual time of the stop of write, which leads to a threshold voltage larger than a scheduled value, and gives rise to a drawback in that the dispersion in the threshold voltage after write has a large value.
Further, the verification of the threshold voltage is carried out concurrent with write, rather than done in accordance with the normal read mode. Accordingly, the conditions such as the voltages to be applied to the control gate and the drain of the memory cell transistor are different at the time of threshold detection and at the time of read, which may lead to the possibility of having a threshold different from the one necessary at the time of read.
Furthermore, according to this system, when data with the lowest threshold are to be written to a memory cell of a multilevel system with more than three levels, there also arises a problem of having a large dispersion in the threshold caused by the overshot writing due to the fast change in the write current. This is caused by the fact that the change in the write current is large in the initial stage and decreases gradually as writing proceeds.